Single-Event Performance and Layout Optimization of Flip-Flops in a 28-nm Bulk Technology
| Autor: | N. J. Gaspard, S. Jagannathan, M. Bounasser, Daniel Loveless, K. Lilja, J. Holst, S.-J. Wen, Rick Wong, Bharat L. Bhuva |
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| Rok vydání: | 2013 |
| Předmět: |
Standard cell
Nuclear and High Energy Physics Engineering business.industry Page layout Hardware_PERFORMANCEANDRELIABILITY FLOPS computer.software_genre Integrated circuit layout Circuit extraction Logic synthesis Nuclear Energy and Engineering CMOS Hardware_INTEGRATEDCIRCUITS Electronic engineering Electrical and Electronic Engineering Physical design business computer Hardware_LOGICDESIGN |
| Zdroj: | IEEE Transactions on Nuclear Science. 60:2782-2788 |
| ISSN: | 1558-1578 0018-9499 |
| DOI: | 10.1109/tns.2013.2273437 |
| Popis: | Alpha, neutron, and heavy-ion single-event measurements were performed on both high-performance and hardened flip-flop designs in a 28-nm bulk CMOS technology. The experimental results agree very well with simulation predictions and confirm that event error rates can be reduced dramatically using effective layout design. |
| Databáze: | OpenAIRE |
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