| Popis: |
This paper presents a novel radix-4 Booth multiplier. A conventional Booth multiplier consists of the Booth encoder, the partial-product summation tree, and the canypropagate adder. Different schemes are addressed to improve the area and circuit speed effectively. A novel modified Booth encodeddecoder is proposed and the summation column is compressed by the proposed MFAr. The proposed design is simulated by Synopsys and Apollo. It results 20% area reduction, 17%&-24% power decrease, and 15% reduction of the delay time of the critical path. |
