Fsm Driven NON-Linear Transistion Based Lfsr TPG for Improved Fault Coverage in BIST Application
| Autor: | Sowmiya G, Malarvizhi G |
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| Rok vydání: | 2022 |
| Zdroj: | ECS Transactions. 107:1317-1326 |
| ISSN: | 1938-6737 1938-5862 |
| DOI: | 10.1149/10701.1317ecst |
| Popis: | The Test pattern generator (TPGs) is one of the computationally intensive and performance centric computational block in BIST applications and has been investigated in many existing works to maximize its contribution towards testing the digital circuits; however, design constraints associated to the system leads significant improvements in TPG model. This paper proposes energy efficient FSM state transition-based LFSR TPG to formulate test patterns with maximum length and randomness. Here LFSR generated test patterns generated from conventional LFSR reseeding model with fixed polynomial configuration is decomposed into smaller units and follows FSM encoding to convert into multiple independent test vector blocks. The concatenation of these encoded vector blocks offers improved test vectors which includes transitional and non- transitional encoded values to regulate the overall switching activity. According to the power constrains each binary positions of test vectors are weighted to control certain bit transitions which can significantly optimize the dynamic power consumption during testing process. Finally, FSM controller is used to control state transition in addition to the variable clock to maximize the randomness randomization characteristics of LFSR. Here both clock rate and number state in FSM machine can be dynamically changed to modify the LFSR statistics in accordance with BIST requirements. |
| Databáze: | OpenAIRE |
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