Implementation of parallel-pipeline H.265 CABAC decoder on FPGA
| Autor: | Menarsri Wahiba, Belhadj Aichouche, Skoudarli Abdellah |
|---|---|
| Rok vydání: | 2017 |
| Předmět: |
High-definition television
Computer science business.industry Lookup table VHDL Codec Entropy encoding Hardware_ARITHMETICANDLOGICSTRUCTURES Field-programmable gate array business computer Context-adaptive binary arithmetic coding Computer hardware Coding (social sciences) computer.programming_language |
| Zdroj: | 2017 First International Conference on Embedded & Distributed Systems (EDiS). |
| DOI: | 10.1109/edis.2017.8284037 |
| Popis: | Ultra High Definition Television (UHDTV) imposes extremely high throughput requirement on video codec's based on High Efficiency Video Coding (H.265/HEVC). Context-based adaptive binary arithmetic coding (CABAC) is specified as the single operation mode for entropy coding in HEVC. Parallel and pipeline processing can be used to increase the throughput for higher performance and decrease the path delay. This paper proposes a pipeline and parallel CABAC decoder architecture adaptive to HEVC syntax elements, In order to reduce the critical path delay, we stored the RangeLps LUT and LZ LUT in the same memory and we exploit different techniques of optimization. The implementation can process 1,5 bins/cycle when operate at 133,31 MHz and improved high throughput of 200Mbin/s for parallel decoder and process 1.49 bins/cycle when operate at 134.2 MHz with throughput of 200Mbin/s for pipeline decoder. The critical path delay is optimized compared to the serial process and the architecture is coded using VHDL language, simulated and synthesized using Xilinx tools with virtex4 xc4vsx25-12ff668 card. |
| Databáze: | OpenAIRE |
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