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Advanced packaging, including fan-outs, 2.5D and 3D integration is gaining more interests as alternative driving force for performance improvement instead of scaling. A key element for the advanced packaging is interconnection technology between different chips. Flip chip micro-bumping enables electrical connection of different chips with shorter length than that of wire bonding. Although it is promising method for advanced packaging, there are several challenges need to be tackled to obtain robustness stacking below 10 μm pitch. For instance, the mechanical stability of micro-bumps become low due to the shape of the bumps. The bump height uniformity also becomes an issue when the pitches shrunk. In addition, the thermo-compression bonding (TCB) alignment and stacking will require incredibly high accuracy tool. In order to overcome these issues, alternative concept of flip chip bumping structures, which is embedded bump was introduced [1]. In this embedded bump concept, neither top nor bottom surfaces have topography, which improves the mechanical stability. In addition, it can be feasible in high-accuracy TCB process. One of the challenge for this concept is to planarize Sn bumps and polymer. The well-known method for material planarization in CMOS technology is chemical mechanical polishing (CMP). However, optimization of polishing on soft adhesive polymer and metal Sn bump requires comprehensive CMP development. On the other hand, pure machining process such as flat milling has wider range of process window. Therefore, we are investigating to apply a single diamond flat milling process, so called surface planer, for this embedded bump concept. The surface planer process is able to mechanically remove polymer top surface and bumps by a diamond bit. In the presentation, we will report characterization results of surface planer process for embedded bump concept. In addition, the stacking performance on 10 μm pitch bumps are shown. The middle images in the figure show that the planarized adhesive polymer and 10 μm pitch bump (top: schematic image, bottom: actual cross-sectional FIB image). The step height between bump and polymer is about 200 nm. By the planarization process, 10 μm pitch of Sn bumps can be connected by thermal compression bonding with minimum misalignment. By this feasibility study of polymer/bump planarization process, compatibility and challenges of embedded bump concept were laid out. [1] Jaber derakhshandeh et al,” 3D Stacking Using Bump-Less Process for Sub 10um Pitch Interconnects” ECTC2016 Figure 1 |
