An Experimental Study on the Effect of Asymmetric Memory Latency of New Memory on Application Performance
| Autor: | Young Je Moon, J. Hyun Kim, Sam H. Noh |
|---|---|
| Rok vydání: | 2016 |
| Předmět: |
010302 applied physics
Hardware_MEMORYSTRUCTURES business.industry Computer science Cache-only memory architecture Registered memory Semiconductor memory Memory bus 02 engineering and technology computer.software_genre 01 natural sciences Memory controller CAS latency 020202 computer hardware & architecture Embedded system 0103 physical sciences 0202 electrical engineering electronic engineering information engineering Operating system Interleaved memory Non-volatile random-access memory business computer |
| Zdroj: | MASCOTS |
| DOI: | 10.1109/mascots.2016.40 |
| Popis: | As DRAM reaches its density limitation, various new memory technologies such as STT-RAM and PCM are emerging as contenders for next generation memory. As these new types of memory, which we refer to as New Memory (NM), are byte addressable and nonvolatile, they are anticipated to, partially or wholly, take on the role of main memory and storage. The goal of this study is to evaluate how the read/write latency gap between the DRAM and NM and the asymmetric read and write latency of NM will affect the performance of applications. To this end, using an in-house ARM based embedded system that allows us to individually adjust the read and write latency. First, we use controlled, synthetic workloads to evaluate the latency effects. The main finding here, among others, is that write latency has little effect on performance due to various hardware mechanisms employed in current cache hardware. We then run the Stream, LMbench and PARSEC 3.0 benchmarks that represent real life applications with various memory latency settings. We find that write latency has virtually no effect and the effect of read latency is limited only to applications with very low cache hit rates. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
|