A design for FPGA implementation of the probabilistic neural network

Autor:	A. Zaknich, G. Minchin
Rok vydání:	2003
Předmět:	Probabilistic neural network Theoretical computer science Logic synthesis Artificial neural network Computer engineering Gate array Computer science Logic gate Probabilistic logic Fixed point Field-programmable gate array Classifier (UML)
Zdroj:	ICONIP'99. ANZIIS'99 & ANNES'99 & ACNN'99. 6th International Conference on Neural Information Processing. Proceedings (Cat. No.99EX378).
DOI:	10.1109/iconip.1999.845654
Popis:	A design concept is introduced for the implementation of the probabilistic neural network classifier using standard binary field programmable gate array logic. It is an efficient hardware design concept which substitutes fixed point binary valued vector components for real valued ones and uses a top hat spherical basis function in conjunction with a city block distance measure without significantly affecting classifier performance for some practical problems.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::1a6d794015b0070b36d5aead77808d27 https://doi.org/10.1109/iconip.1999.845654 Zobrazit plný text záznamu