A Device Design for 5 nm Logic FinFET Technology
| Autor: | Yuhang Zhao, Yu Ding, Shang Enming, Shoumian Chen, Xin Luo, Hu Shaojian |
|---|---|
| Rok vydání: | 2020 |
| Předmět: |
010302 applied physics
Computer science Process capability Process (computing) 02 engineering and technology Ring oscillator 021001 nanoscience & nanotechnology 01 natural sciences Logic synthesis 0103 physical sciences Electronic engineering Key (cryptography) System on a chip Device simulation 0210 nano-technology |
| Zdroj: | 2020 China Semiconductor Technology International Conference (CSTIC). |
| DOI: | 10.1109/cstic49141.2020.9282491 |
| Popis: | In this paper, we proposed a 5 nm FINFET device, which is based on typical 5 nm logic design rules. We have performed an optimization on the process parameters and iterate through device simulation with the consideration of current process capability. Based on our preferred device architecture, we provide our process key dimensions, and simulated device DC/AC performance, and some parasitic parameters. As a part of the final evaluation, Ring Oscillator (RO) simulation result has been checked, which demonstrates that the Performance Per Area (PPA) is close to industry reference 5 nm performance. |
| Databáze: | OpenAIRE |
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