Understanding the Design Trade-Offs of Hybrid Flash Controllers
| Autor: | Nikolaos Papandreou, Haris Pozidis, Sasa Tomic, Radu Stoica, Nikolas Ioannou, Roman A. Pletka |
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| Rok vydání: | 2019 |
| Předmět: |
Hardware_MEMORYSTRUCTURES
Computer science Trade offs NAND gate High density 020206 networking & telecommunications Workload 02 engineering and technology 020202 computer hardware & architecture Data modeling Data flow diagram Computer engineering 0202 electrical engineering electronic engineering information engineering Cache Latency (engineering) |
| Zdroj: | MASCOTS |
| Popis: | Over the last few years, NAND flash manufacturers have steadily increased the number of bits stored per cell to achieve significant cost reductions. However, the increased density does not come without drawbacks. All key flash performance metrics, including latency and endurance, significantly degrade as bit density increases. Particularly, sustained write throughput is the worst affected as writes are roughly one order of magnitude slower than reads and further require precursory block erases in the background. As a result, many recent flash controllers operate flash blocks both in single-bit (high endurance and performance) and in multi-bit (high density) mode. In theory, such hybrid controllers are a great way of hiding flash technology limitations. A controller can use a small percentage of the flash blocks in single-bit mode as a cache which allows orders of magnitude higher write bandwidth and endurance in environments where the access patterns of the workload are skewed and bursty. In practice, however, many devices fall short of expectations when write performance varies significantly and utilization increases. We argue that a principled approach is required to understand the design trade-offs of hybrid NAND flash controllers. To this end, we develop a modeling framework for estimating the performance and endurance of hybrid controllers. The modeling framework computes the internal data movement generated by a hybrid controller by relying on advanced analytical models that offer both accurate and fast predictions. The data flow is then translated into higher-level metrics that quantify upper bounds for the overall performance of an SSD such as write throughput, latency, and device endurance. Using our modeling framework, we compare different controller architectures, identify their strong and weak points, and show that there is room to improve the efficiency of the hybrid controllers used today. |
| Databáze: | OpenAIRE |
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