A simple method to improve the noise margin of III-V DCFL Digital circuit coupling diode FET logic
| Autor: | S.I. Long, A.T. Yuen, Long Yang |
|---|---|
| Rok vydání: | 1986 |
| Předmět: |
Digital electronics
Engineering business.industry Electrical engineering Hardware_PERFORMANCEANDRELIABILITY Transistor–transistor logic Noise (electronics) Electronic Optical and Magnetic Materials Noise margin Logic gate Hardware_INTEGRATEDCIRCUITS Electronic engineering MESFET Field-effect transistor Electrical and Electronic Engineering business Hardware_LOGICDESIGN Diode |
| Zdroj: | IEEE Electron Device Letters. 7:145-148 |
| ISSN: | 0741-3106 |
| Popis: | This paper proposes a novel method to increase the noise margins achievable with III-V DCFL digital circuits. The idea is to increase the forward-biased potential obtainable on the gate of the enhancement device before substantial conduction occurs. The method we propose is to simply add a diode in series with the gate. Circuit simulations (MESFET and HFET) and device theory are given to support the feasibility of the Coupling Diode FET Logic (CDFL). A novel device structure, compatible with the semiconductor-gate HFET [3], also will be given. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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