Graph based fault model definition for bus testing

Autor:	Mohamad Hashem Haghbayan, Elmira Karimi, Mahmoud Tabandeh, Adele Maleki
Rok vydání:	2013
Předmět:	Stuck-at fault Computer science Graph based Hardware_INTEGRATEDCIRCUITS System on a chip Graph theory Hardware_PERFORMANCEANDRELIABILITY Parallel computing Fault model Fault (power engineering) Graph model Hardware_LOGICDESIGN
Zdroj:	VLSI-SoC
Popis:	In this paper we present a new fault model for testing standard On-Chip buses using a graph model. This method will be optimized for speed of testing. Using AMBA-AHB as the experimental result, the proposed fault model shows efficiency in comparison with corresponding stuck-at fault testing.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::189acb974b9e125bb616c4f6e8846ed5 https://doi.org/10.1109/vlsi-soc.2013.6673246 Zobrazit plný text záznamu