Resonant-Clock Design for a Power-Efficient, High-Volume x86-64 Microprocessor

Autor:	A. Ishii, Marios C. Papaefthymiou, Charles Ouyang, Visvesh S. Sathe, Srikanth Arekapudi, Samuel D. Naffziger
Rok vydání:	2013
Předmět:	Engineering business.industry Underclocking Clock gating Integrated circuit design law.invention Power (physics) Microprocessor law Low-power electronics Electronic engineering Electrical and Electronic Engineering business Testability CPU multiplier
Zdroj:	ISSCC
ISSN:	1558-173X 0018-9200
DOI:	10.1109/jssc.2012.2218068
Popis:	AMD's 4+ GHz x86–64 core codenamed “Piledriver” employs resonant clocking [1–4] to reduce clock distribution power up to 24% while maintaining a low clock-skew target. To support testability and robust operation at the wide range of operating frequencies required of a commercial processor, the clock system operates in two modes: direct-drive (cclk) and resonant (rclk). Leveraging favorable factors such as the availability of two thick top-level metals, high operating frequency, clock-load density, and the existing clock-design methodology [5], the rclk mode was designed to enable both reduced average power dissipation and improved peak-power-constrained performance, with minimal area impact. This work represents a volume production-enabled implementation of resonant clock technology, and is plan of record for mid-2012 product offerings.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::1884f195f606eb2ccde8150b4e58b1be https://doi.org/10.1109/jssc.2012.2218068 Zobrazit plný text záznamu