Autor: |
Jan Henning Mueller, Stefan Heinen, Sven Schenk, Richard Leys, Ulrich Bruening, Ye Zhang, Bastian Mohr |
Rok vydání: |
2013 |
Předmět: |
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Zdroj: |
Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME). |
DOI: |
10.1109/prime.2013.6603153 |
Popis: |
This paper presents a high-speed serial PLL-less interface suitable for usage in mobile transmitters. The interface uses current mode signaling to reduce both ground bouncing and the crosstalk impact on the mobile frontend. A digital controlled delay line is employed to adjust the sampling point of the highspeed serial clock. The data is 8b/10b encoded for word recovery and signaling of configuration packets. The interface is self-initializing and distinguishes between signal and configuration data. It consists of three lanes from the FPGA to the ASIC and one lane in backward direction to debug the internal ASIC signals. The interface is able to transfer up to 1.6 Gbit/s per lane. It consumes 3mA from a 1.2V supply. |
Databáze: |
OpenAIRE |
Externí odkaz: |
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