Autor: |
Chaoxiang Yang, Ziqiang Wang, Zhijun Wang, Chun Zhang, Xiang Xie, Wenao Xie |
Rok vydání: |
2017 |
Předmět: |
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Zdroj: |
2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC). |
DOI: |
10.1109/edssc.2017.8126494 |
Popis: |
The 10Gbase-KR protocol is widely used to accomplish the high speed data conversion in the Ethernet area. This paper presents a design of the critical controller in the physical coding sublayer based on the 10Gbase-KR. In order to satisfy the demand of the high speed data conversion, the scrambler and descrambler are specially designed to work in a parallel mode. The post-synthesis simulation results demonstrate that the adapted parallel scrambler and descrambler work well in the whole PCS system with the MAC and PMA sublayer. |
Databáze: |
OpenAIRE |
Externí odkaz: |
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