Design of Convolution Neural Network Accelerator Based on FPGA

Autor:	Qian Yi
Rok vydání:	2021
Předmět:	business.industry Computer science Multiple buffering Perspective (graphical) Function (mathematics) business Field-programmable gate array Convolutional neural network Computer hardware Object detection Convolution
Zdroj:	2021 IEEE 2nd International Conference on Big Data, Artificial Intelligence and Internet of Things Engineering (ICBAIE).
DOI:	10.1109/icbaie52039.2021.9389880
Popis:	In this paper, aiming at the embedded and realtime target detection platform, from the perspective of highspeed hardware implementation, the target detection algorithm based on Mobilenet-SSD is analyzed. The CNN accelerator based on FPGA is designed, using hardware optimization techniques such as parallel, pipelining and double buffering. The function verification and performance test are carried out on GVI Cxz7100 development board. The test results show that the design function is correct, and the processing speed is better than that of PC.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::1772a4dd87f2bcfd584f9fbfd8736a71 https://doi.org/10.1109/icbaie52039.2021.9389880 Zobrazit plný text záznamu