Design and synthesis of reversible arithmetic and Logic Unit (ALU)
| Autor: | Nor Syahira Mohd Mahayadin, Alpha Agape Gopalai, Adib Kabir Chowdhury, Ashutosh Kumar Singh, Lenin Gopal |
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| Rok vydání: | 2014 |
| Předmět: |
Adder
Pass transistor logic Computer science Circuit design Logic family Propagation delay Arithmetic logic unit Logic synthesis Logic gate Reversible computing Hardware_ARITHMETICANDLOGICSTRUCTURES Arithmetic Altera Quartus Three-input universal logic gate Hardware_LOGICDESIGN Logic optimization Register-transfer level |
| Zdroj: | 2014 International Conference on Computer, Communications, and Control Technology (I4CT). |
| DOI: | 10.1109/i4ct.2014.6914191 |
| Popis: | In low power circuit design, reversible computing has become one of the most efficient and prominent techniques in recent years. In this paper, reversible Arithmetic and Logic Unit (ALU) is designed to show its major implications on the Central Processing Unit (CPU).In this paper, two types of reversible ALU designs are proposed and verified using Altera Quartus II software. In the proposed designs, eight arithmetic and four logical operations are performed. In the proposed design 1, Peres Full Adder Gate (PFAG) is used in reversible ALU design and HNG gate is used as an adder logic circuit in the proposed ALU design 2. Both proposed designs are analysed and compared in terms of number of gates count, garbage output, quantum cost and propagation delay. The simulation results show that the proposed reversible ALU design 2 outperforms the proposed reversible ALU design 1 and conventional ALU design. |
| Databáze: | OpenAIRE |
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