Design and implementation of Phase Locked Loop on 180nm Technology node

Autor:	T. C. Thanuja, K V Kumaraswamy, Sanjana Hokrani
Rok vydání:	2018
Předmět:	Phase-locked loop Voltage-controlled oscillator Computer science Schmitt trigger business.industry Low-pass filter Charge pump Electrical engineering Node (circuits) Communications system business Phase frequency detector
Zdroj:	2018 4th International Conference for Convergence in Technology (I2CT).
DOI:	10.1109/i2ct42659.2018.9057996
Popis:	This paper signifies the transient analysis of the PLL and is implemented in cadence tool using 180nm technology node. Frequency is expected to be in GHz range for present communication systems to increase the speed and therefore PLL is designed to produce the frequency in GHz range. The designed PLL consists of Phase frequency detector/Charge pump (PFD/CP), second order Low pass filter (LPF) and Schmitt trigger based current starved voltage controlled oscillator (CSVCO). PLL is designed to achieve a stable frequency output. The designed PLL produces 1.084 GHz with 2.382mW of average power consumption.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::1686a8f4ea1e34274f6b9b83d5e09e58 https://doi.org/10.1109/i2ct42659.2018.9057996 Zobrazit plný text záznamu