A 240-mW 2.1-GS/s 52-dB SNDR Pipeline ADC Using MDAC Equalization

Autor:	Chun-Ying Chen, Shauhyuarn Sean Tsai, Chun-Sheng Huang, Wenbo Liu, Tianwei Li, Loke Kun Tan, Bryan Juo-Jung Hung, Steven T. Jaffe, Jiangfeng Wu, Hung Vu, Wei-Ta Shih, Binning Chen, Lin He, Hing T. Hung
Rok vydání:	2013
Předmět:	CMOS Finite impulse response Computer science Bandwidth (signal processing) Hardware_INTEGRATEDCIRCUITS Electronic engineering Correction technique Successive approximation ADC Hardware_ARITHMETICANDLOGICSTRUCTURES Electrical and Electronic Engineering Residue amplifier
Zdroj:	IEEE Journal of Solid-State Circuits. 48:1818-1828
ISSN:	1558-173X 0018-9200
Popis:	This paper introduces multiplying digital-to-analog converter (MDAC) equalization, a digital correction technique for pipeline ADCs that corrects MDAC gain, settling, and other dynamic errors using successive digital FIR filters operating on sub-ADC output samples. This technique reduces the required MDAC residue amplifier (RA) bandwidth relative to the sampling frequency, thereby reducing ADC power. MDAC equalization is demonstrated in a 240-mW 2.1-GS/s ping-pong pipeline ADC in 40-nm CMOS where MDAC RA power is reduced from 175 to 53 mW by 70%. The ADC achieves 58 dB SNR and 52 dB SNDR.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::164c742aef13f349ac1dae9a76efb0fd https://doi.org/10.1109/jssc.2013.2259013 Zobrazit plný text záznamu