| Popis: |
Due to the buried oxide structure, SOI MOS devices may suffer from floating-body related kink effects [1]. For nanometer MOS devices with a thin gate oxide, gate tunneling leakage current cannot be neglected [2]. In this paper, analysis of the floating-body-effect-related gate tunneling leakage current phenomenon of the 40nm PD NMOS device using the SPICE bipolar/MOS equivalent circuit approach is reported. Fig. 1 shows the cross section of the 40nm PD SOI NMOS device under study. As shown in the figure, a thin film of 70nm is above a buried oxide of 145nm. The effective channel length is 40nm and the gate oxide thickness is 1.5nm. Experimental measurement and an equivalent circuit approach based on the SPICE bipolar/MOS device models have been used to conduct the study. As shown in Fig. 2, the PD SOI NMOS device could be characterized using the combination of an MOS device with a bipolar device, which is used to account for the function of the parasitic BJT in the thin film. Using the SPICE bipolar/MOS equivalent circuit approach, considering the current conduction mechanism [3], the drain current of the PD SOI NMOS device is composed of the surface channel current (I ch ), the hole current (I h ) generated by the impact ionization (II) in the high electric field region and the collector of the parasitic bipolar device (I C ). The base current (I b ) of the parasitic BJT comes from a portion of the II current (kI h ). The source current (I S ) is composed of the channel current (I ch ), the remaining portion of the II current ((1−k)I h ) and the emitter current (I E ) of the parasitic bipolar device. A portion of the collector current (k'I C ) goes to the high electric field region, also triggering II. The distributed gate tunneling leakage current is a function of the local vertical electric field in the gate oxide. From the partitioned model [2], the lumped gate-source/drain tunneling leakage current (I GS /I GD ) could be found. Total gate tunneling leakage current is the sum of the lumped gate-source/drain components- I G =I GS +I GD . Using the equivalent circuit based on the SPICE bipolar/MOS devices, the floating-body-effect-related gate tunneling leakage current could be analyzed assuming the existing models of the bipolar and the MOS devices. Fig. 3 shows the gate current versus the drain voltage of the 40nm PD SOI NMOS device based on the experimentally measured data and the SPICE bipolar/MOS equivalent circuit approach with and without considering the bipolar device. As shown in the figure, when the drain voltage increases, the gate tunneling leakage current decreases. When the gate voltage decreases, the gate tunneling leakage current also decreases. As the gate voltage becomes small, the gate tunneling leakage current becomes very small, possibly negative, at a large drain voltage. Using the SPICE bipolar/MOS equivalent circuit approach considering the bipolar device, the gate tunneling leakage current (I G ) behavior especially at a large drain voltage could be predicted. Without considering the bipolar device, I G is over-estimated at a large V D . The trend on the gate tunneling leakage current as shown in Fig. 3 is closely correlated to the kink behavior [4], which is also due to the floating body effect of the PD SOI NMOS device. Fig. 4 shows (a) the base voltage (V be ) of the parasitic bipolar device and (b) the drain current versus the drain voltage of the 40nm PD SOI NMOS device, extracted from the SPICE simulation results using the SPICE bipolar/MOS equivalent circuit approach. As shown in the figure, at a larger V G , the base voltage rises later, which indicates a slower turn-on of the bipolar device, confirming the trend as the result by 2D device simulation [4]. At a larger V G , the high electric field region in the lateral channel direction at the front Si/SiO 2 interface shrinks. Thus, a reduced II leads to a weaker function of the parasitic bipolar device. On the other hand, as indicated in the figure, a smaller V G such as 0.4V brings in an earlier turn-on of the parasitic bipolar device due to a stronger II, which also affects the gate tunneling leakage current as the floating body effect. Fig. 5 shows the perpendicular electric field at the interface along the path around the three U-shaped edges of the poly gate of the 40nm PD SOI NMOS device, biased at V G =0.4V and V D =0.2V/1.2V, based on the 2D simulation results. As shown in the figure, when V D is large (1.2V), in the path close to the drain, the electric field is substantially reduced, possibly becoming negative. As a result, the corresponding local gate tunneling leakage current reverses its direction in this region- I G reduces substantially at a large V D . More insight into the mechanism of the gate tunneling leakage current could be obtained by studying the partitioned gate tunneling leakage current components. Lumped gate-source/gate-drain tunneling leakage currents I GS /I GD , which could be obtained by partitioning the distributed gate tunneling leakage current, is composed of the poly edge and the center channel components-I GS =I gs +I gcs /I GD =I gd +I gcd . Fig. 6 shows I gs /I gd and I gcs /I gcd versus drain voltage of the 40nm PD SOI NMOS device, extracted from the SPICE simulation results using the bipolar/MOS equivalent circuit approach. From the figure, the edge component of the gate-source/ gate-drain leakage current (I gs /I gd ), which is much smaller than that of the center channel one (I gcs /I gcd ), could become negative at a large V D due to the reverse vertical electric field near the drain. The dominant component of the gate tunneling leakage current in the center channel region (I gcs /I gcd ) is strongly dependent on V G . A smaller V G leads to a larger II region, makes a stronger parasitic bipolar device with a larger base voltage at a large V D - the floating body effect. As a result, the voltage difference between the gate and the thin film drops. Therefore, the vertical electric field in the gate oxide, especially near the drain, is reduced substantially. I gcs /I gcd and thus I G become smaller- the floating-body induced gate tunneling leakage current effect. Using the SPICE bipolar/MOS equivalent circuit approach, this effect could be analyzed in a straightforward way. |
