Memory-Logic Hybrid Gate With 3-D Stackable Complementary Latches
| Autor: | Jonathan Chang, Chrong Jung Lin, Yue-Der Chih, Ya-Chin King, Chieh Lee |
|---|---|
| Rok vydání: | 2020 |
| Předmět: |
010302 applied physics
Resistive touchscreen Materials science business.industry 01 natural sciences Complementary pair Electronic Optical and Magnetic Materials Resistive random-access memory Power (physics) CLs upper limits CMOS 0103 physical sciences Optoelectronics Data restoration Electrical and Electronic Engineering business Voltage |
| Zdroj: | IEEE Transactions on Electron Devices. 67:3109-3114 |
| ISSN: | 1557-9646 0018-9383 |
| DOI: | 10.1109/ted.2020.3000737 |
| Popis: | In this article, a single-layer complementary latch (CL) and one multilayer CL which are fully compatible with standard FinFET CMOS processes are characterized and their applications are extensively discussed. Through the complementary pair with the 3-D stackable twin-bit resistive random-access memory (RRAM) which consists of a TaON-based resistive film, the CLs feature great area efficiency and stable output responses. By measurement, the characteristics of the 3-D stackable twin-bit RRAM are discussed. Besides, the power, output voltage distribution, and data restoration time of the CLs are analyzed and compared. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
|