| Autor: |
Y. Amar Babu, G. M. V. Prasad, John Bedford Solomon |
| Rok vydání: |
2017 |
| Předmět: |
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| Zdroj: |
Advances in Intelligent Systems and Computing ISBN: 9789811068744 |
| DOI: |
10.1007/978-981-10-6875-1_53 |
| Popis: |
As VLSI technology is growing exponentially, silicon chips can accommodate more cores on a chip and this will lead to very high computational power but poor communication among on-chip processors and memory. To overcome this, we proposed spatial division multiplexing based network-on-chip with the modified network interface. Proposed network interface provides high throughput with the optimized area and consume very low power. We have evaluated proposed SDM-based NoC (network-on-chip) with high-performance network interface for 2 × 2 network which occupied only 4% of resources on Xilinx Spartan6 SP605 FPGA. We modeled the network interface using VHDL and multicore platform is prepared by using Xilinx EDK and verified computationally complex application at 88.6 MHz processor frequency but achieved high throughput. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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