A fully integrated low noise RF frequency synthesizer design for mobile communication application

Autor:	Seog-Jun Lee, Beomsup Kim, Kwyro Lee
Rok vydání:	2002
Předmět:	Frequency synthesizer Engineering business.industry Electrical engineering dBc Hardware_PERFORMANCEANDRELIABILITY Decoupling capacitor Phase-locked loop Direct digital synthesizer Phase noise Hardware_INTEGRATEDCIRCUITS Electronic engineering Radio frequency business Electronic filter
Zdroj:	1996 Symposium on VLSI Circuits. Digest of Technical Papers.
DOI:	10.1109/vlsic.1996.507714
Popis:	A fully monolithic PLL frequency synthesizer circuit implemented in a 0.8 /spl mu/m CMOS technology is presented. The measured result shows a frequency range of 700 MHz to 1 GHz with -100 dBc/Hz phase noise at a 1 MHz carrier offset. The test chip consumes 125 mW at maximum frequency from a 5 V supply. No external components are used except a passive filter and supply decoupling capacitors.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::14e1914414ad64dab52c44577d6eca3c https://doi.org/10.1109/vlsic.1996.507714 Zobrazit plný text záznamu