| Autor: |
Mark D. Jacunski, P. K. Lane, Michael A. Roberge, Dale E. Pontius, S. Sliva, John A. Fifield, Robert E. Busch, Adrian J. Paparelli, Darren L. Anand, Gary Pomichter, Matthew C. Lanahan |
| Rok vydání: |
2010 |
| Předmět: |
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| Zdroj: |
CICC |
| DOI: |
10.1109/cicc.2010.5617634 |
| Popis: |
A family of embedded DRAMs which are fabricated in 45nm SOI technology is presented. The fast eDRAM has 64 b/BL and achieves a random cycle time of 1.3ns for V DD = 1.00V and typical process. The dense eDRAM has 128 b/BL and operates in multi-bank modes up to 1.67GHz for V DD = 1.0V and nominal process. The staggered - folded BL architecture with BL twisting over both the array and SAs is described as well as a novel wordline timer which generates a 75% duty cycle signal from a 50% duty cycle clock. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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