A 1.0GHz multi-banked embedded DRAM in 65nm CMOS featuring concurrent refresh and hierarchical BIST

Autor:	J. Paparelli, John A. Fifield, Dale E. Pontius, Michael A. Roberge, S. Sliva, Kevin W. Gorman, Jeffrey H. Dreibelbis, Darren L. Anand, J. Covino, G. Pomichter, Mark D. Jacunski
Rok vydání:	2007
Předmět:	Engineering business.industry Deep trench law.invention Capacitor CMOS Built-in self-test law Gate oxide Transfer (computing) Embedded system Macro business Dram
Zdroj:	CICC
DOI:	10.1109/cicc.2007.4405849
Popis:	An embedded DRAM macro fabricated in 65 nm CMOS achieves 1.0 GHz multi-banked operation at 1.0 V yielding 584 Gbits/sec. The array utilizes a 0.1 1 mum2 cell with 20 fF deep trench capacitor and 2.2 nm gate oxide transfer gate. Concurrent refresh allows for high availability via a second bank address. At-speed test and repair is accomplished with a new hierarchical BIST architecture. Measured random cycle time exceeds 333 MHz at 1.0 V with functional operation from 750 mV to 1.5 V and densities up to 36.5 Mbits.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::14541abf360e7654127a45f03b2a7e54 https://doi.org/10.1109/cicc.2007.4405849 Zobrazit plný text záznamu