A low jitter burst-mode clock and data recovery circuit with two symmetric VCO's
| Autor: | Bum-Hee Choi, Jin-Ku Kang, Kyung-Sub Son |
|---|---|
| Rok vydání: | 2016 |
| Předmět: |
business.industry
Computer science 020208 electrical & electronic engineering 020206 networking & telecommunications Burst mode clock and data recovery 02 engineering and technology Data recovery Voltage-controlled oscillator Low jitter Timing margin Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Electronic engineering Cmos process business Cell based Jitter |
| Zdroj: | APCCAS |
| Popis: | This paper presents a burst-mode clock and data recovery (CDR) circuit based on two symmetric VCO's. Compared with the conventional structure with a T/2 delay cell based approach, the proposed structure shows the better re timing margin without any delay unit for the timing control. The proposed circuit is designed and simulated in 350nm CMOS process. The simulation of the proposed CDR showed the data recovery at 1.6 Gb/s with 27-l pattern with peak-to-peak jitter of 5.5ps. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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