A 0.5-W 64-kilobyte snoopy cache memory with pseudo two-port operation

Autor:	T. Kobayashi, Y. Biwaki, M. Kobayashi, Koichi Kobayashi, Kazutaka Nogami, Kazuhiro Sawada, H. Nohara, Tsukasa Shirotori, Yukihiro Fujimoto
Rok vydání:	1991
Předmět:	Snoopy cache Engineering Hardware_MEMORYSTRUCTURES Comparator business.industry Parallel computing MESIF protocol Non-uniform memory access CMOS Write-once Hardware_INTEGRATEDCIRCUITS Kilobyte Cache Electrical and Electronic Engineering business
Zdroj:	IEEE Journal of Solid-State Circuits. 26:1586-1592
ISSN:	0018-9200
DOI:	10.1109/4.98976
Popis:	A 64-kbyte snoopy cache memory was developed. The modified double word-line architecture with word-line buffers resulted in a large-size memory and a time-multiplex snoop operation by the pseudo-two-port method with a single-port cell. The flexible expandability was achieved by cascading multiple cache memories. The device was successfully implemented with 1.0- mu m double-polysilicon and double-metal CMOS technology. Low-power sense amplifiers and comparators limited power dissipation to 0.5 W at 40 MHz. >
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::13aa36d24c89d99fda4e9bbc04564384 https://doi.org/10.1109/4.98976 Zobrazit plný text záznamu