| Autor: |
Zhou Peng, Mehraeen Esmaeil, Jahangir Rahil, S. Kanwar Shamsher, Das Proteeti, Wei Yunlin, Wu Lijun, İlker Saygılı Eyüp, Faruk Hossen Md., Kudrat-E-Zahan Md., L. Roe Amy, Song Pengfei, Hangül Ceren, Berker Karaüzüm Sibel, Javaherian Mohammad, Lin Hao, Demir-Dora Devrim, Lv Hao, Gupta Shruti, Sobarzo-Sánchez Eduardo, Shang Junjie, Shahlaee Fatemeh, Ebrahimnejad Pedram, Rahimi Sajad, Ghadimi Maryam, Hoque Munshi Najmul, Sadeghi-Ghadi Zaynab, Ali Mahjoub Mohammad, Tripathi Neeraj, Hayati Bagher, Ebrahimi Pouneh, Qin Kunhao, Çetin Zafer, Shan Yan, Zhang Dongfang, Ma Yongkai, Maitra Subhasis, Sabatier Jean-Marc, Mudakir Fazili Mohammad, Evcili Gökhan, Najafi Zeinab, Küpeli Akkol Esra, Dao Fu-Ying, Zulfiqar Hasan, Ali Asraf Md., Dadras Omid, Ji Xiuling, Yang Hui, Cui Yinshan, Venkataraman Arvind, Zhu Jie, Chen Wei, Zakaria C. M., Wang Yi, SeyedAlinaghi SeyedAhmad |
| Rok vydání: |
2022 |
| Předmět: |
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| Zdroj: |
Micro and Nanosystems. 14:256-262 |
| ISSN: |
1876-4029 |
| DOI: |
10.2174/1876402913666210726170207 |
| Popis: |
Aim: A novel design for non-reversible as well as reversible parity generator and detector in Quantum-dot Cellular Automata (QCA) technology is presented in this research article. Parity generator and detector circuits are reliable error-checking components of a nano-communication system. Objective: The main focus of this research is to design an ultra-low-power fault-tolerant reversible gate implementation of the parity logic function in QCA. An efficient QCA design layout with minimal area, less latency and the least energy dissipation is desired. Methods: The proposed designs are developed using Quantum-dot Cellular Automata (QCA) technology. The circuits are optimized using majority gate reduction and clock zone reduction techniques. Also, the cell-cell interaction technique is employed to further optimize the QCA circuit. To increase the fault tolerance and ultra-low power operation, reversible QCA circuits are designed using cascaded Feynman gates. Results Conclusion: The efficiency of the parity generator and detector is calculated to be more than 25% compared to existing QCA layouts. It is demonstrated in this paper that the proposed circuits perform exceptionally well on every design parameter. The design parameters under consideration are cell count, cell area, complexity, crossover count, latency and energy dissipation. Conclusion: Using reversible logic, a fault-tolerant and defect-sensitive circuit are developed for parity generation and detection. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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