| Popis: |
A novel ADC architecture is introduced with a sampling rate comparable to flash converters, but with reduced power consumption. Broadband active delay circuits pass the input along with a clock through a continuous-time pipeline. Efficient internal buffers eliminate the need for an external driver by providing 15 fF of kickback-free input capacitance. The 5-bit prototype has a 2.5-bit first stage, 1.5-bit second stage, and 2-bit final stage allowing for digital correction of interstage errors. It consumes 47 mW at 7 GS/s in 28-nm CMOS. |
