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We demonstrated a CMOS invertor with a 15 ps propagation delay (tpd) at 77 K. This device uses n+ - p+ double-gate SOI MOSFETs with a gate length (LG) of 0.19 micrometers and a gate oxide thickness (tox) around 9 nm. The channel doping concentration of this device is maintained as low as 1015 cm-3 even in the deep submicron gate length regime while maintaining short channel immunity. Therefore, the decreased phonon scattering due to the cryogenic operation causes a significant increase in mobility, which leads to smaller tpd than any other reported values for a given LG. Although the threshold voltage (Vth) increases with a decrease in temperature, we can adjust it for cryogenic operation by controlling tox and the SOI thicknesses (tSi).© (1995) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only. |
