Autor: |
J. Scarpulla, K.P. MacWilliams, D.J. Swanson, L.E. Lowry |
Rok vydání: |
2003 |
Předmět: |
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Zdroj: |
1992 Symposium on VLSI Technology Digest of Technical Papers. |
DOI: |
10.1109/vlsit.1992.200668 |
Popis: |
It is pointed out that wafer-mapping of physical stresses by X-ray diffraction of a silicided CMOS process shows regions of both very high and low stress levels. The regions of high stress consistently have increased subthreshold slopes and are much more sensitive to hot-carrier induced threshold voltage shifts. Hot carrier lifetime variations over two orders of magnitude are explicitly shown to correlate with the physical stress level within a given highly stressed wafer. To optimally deliver maximum device performance with high reliability, it is essential that physical stress levels be measured, understood, and minimized. > |
Databáze: |
OpenAIRE |
Externí odkaz: |
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