Test Architecture for Fine Grained Capture Power Reduction
| Autor: | R. Iris Bahar, Yi Sun, Theodore W. Manikas, Matan Segal, Jennifer Dworak, Lakshmi Ramakrishnan, Kundan Nepal, Hui Jiang |
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| Rok vydání: | 2019 |
| Předmět: |
Computer science
business.industry 020208 electrical & electronic engineering Scan chain 02 engineering and technology Automatic test pattern generation 020202 computer hardware & architecture Power (physics) Test (assessment) Reduction (complexity) Control register Test set Fault coverage 0202 electrical engineering electronic engineering information engineering business Computer hardware |
| Zdroj: | ICECS |
| Popis: | Excessive power during in–field testing can cause multiple issues, including invalidation of the test results, over- heating, and damage to the circuit. In this paper, we evaluate the reduction of capture power when specific segments of a scan chain can be kept from capturing data subject to values stored in a control register. The proposed approach requires no changes to the Automatic Test Pattern Generation (ATPG), no redesign of the circuitry to match a particular test set, and no additional patterns to maintain fault coverage. We will show that our approach can achieve very high capture power reduction-approaching 100% for multiple patterns. |
| Databáze: | OpenAIRE |
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