Performance Analysis of Multipliers Using Modified Gate Diffused Input Technology
| Autor: | Y. G. Praveen Kumar, C. N. Bharath, S. M. Shashank, B. S. Kariyappa |
|---|---|
| Rok vydání: | 2020 |
| Předmět: |
Digital signal processor
Vlsi system design business.industry Computer science 020208 electrical & electronic engineering Electrical engineering 020206 networking & telecommunications 02 engineering and technology Dissipation Computer Science Applications Theoretical Computer Science Power (physics) CMOS Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Input technology Electrical and Electronic Engineering business Wallace tree multiplier Hardware_LOGICDESIGN |
| Zdroj: | IETE Journal of Research. 68:3887-3899 |
| ISSN: | 0974-780X 0377-2063 |
| DOI: | 10.1080/03772063.2020.1782778 |
| Popis: | The primitive constraints in any VLSI system design are power, delay and area. Systems based on CMOS logic consume more power and area. Higher power dissipation will have a direct effect on the lif... |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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