Design Implications of Single Event Transients in a Commercial 45 nm SOI Device Technology
| Autor: | Philip J. Oldiges, Jonathan A. Pellish, A.J. Kleinosowski, Ethan H. Cannon, L. Wissel |
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| Rok vydání: | 2008 |
| Předmět: |
Nuclear and High Energy Physics
Engineering business.industry Event (relativity) Electrical engineering Silicon on insulator Hardware_PERFORMANCEANDRELIABILITY Transient analysis Soft error Nuclear Energy and Engineering Single event upset Hardware_INTEGRATEDCIRCUITS Electronic engineering Hardware_ARITHMETICANDLOGICSTRUCTURES Electrical and Electronic Engineering business Hardware_LOGICDESIGN Electronic circuit |
| Zdroj: | IEEE Transactions on Nuclear Science. 55:3461-3466 |
| ISSN: | 0018-9499 |
| DOI: | 10.1109/tns.2008.2005191 |
| Popis: | This paper presents modeling and measurements of single event transients in a commercial 45 nm SOI device technology. SETs in clock circuits and pass gates can cause upsets in circuit structures hardened against single event upsets. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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