ESD protection for thin gate oxides in 65nm
| Autor: | Peter de Jong, Guido Notermans, Hans van Zwol, Željko Mrčarica, Theo Smedes, Ralph Stephan, Dejan Maksimovic |
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| Rok vydání: | 2010 |
| Předmět: |
Materials science
Electrostatic discharge business.industry Transistor Electrical engineering Condensed Matter Physics Atomic and Molecular Physics and Optics Standard deviation Surfaces Coatings and Films Electronic Optical and Magnetic Materials law.invention Core (optical fiber) law Transmission line Gate oxide Optoelectronics Electrical and Electronic Engineering Safety Risk Reliability and Quality business NMOS logic Transmission-line pulse |
| Zdroj: | Microelectronics Reliability. 50:26-31 |
| ISSN: | 0026-2714 |
| DOI: | 10.1016/j.microrel.2009.09.010 |
| Popis: | Unexpected functional failures were found in the core of an IC, processed in a 65 nm technology with 1.8 nm gate oxide, after Machine Model (MM) testing, although a comprehensive rail-based protection scheme was applied. Failure analysis was performed including Obirch, backside de-processing, and SEM analysis to locate the failure in the gate oxide of several core NMOS transistors. Careful Transmission Line Pulse (TLP) measurements on NMOSTs with 1.8 nm oxides yields a mean BVox = 6.06 V and standard deviation of 0.18 V, after correction for MM test conditions. Comparison with a mean Vt1 = 5.35 V and a standard deviation of 0.15 V for ggNMOSTs shows that the tails of the BVox and Vt1 distributions overlap. This implies that connecting a gate to a drain diffusion does not guarantee adequate protection for a 1.8 nm gate oxide in a 65 nm technology. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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