Machine Learning-Based Approach for Hardware Faults Prediction
Autor: | Omar Eldash, Ashok Kumar, Magdy Bayoumi, Kasem Khalil |
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Rok vydání: | 2020 |
Předmět: |
Comparator
Computer science business.industry Noise (signal processing) Amplifier 020208 electrical & electronic engineering Fast Fourier transform Fault tolerance Hardware_PERFORMANCEANDRELIABILITY 02 engineering and technology Fault (power engineering) Convolutional neural network Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering 020201 artificial intelligence & image processing Electrical and Electronic Engineering business Field-programmable gate array Computer hardware |
Zdroj: | IEEE Transactions on Circuits and Systems I: Regular Papers. 67:3880-3892 |
ISSN: | 1558-0806 1549-8328 |
DOI: | 10.1109/tcsi.2020.3010743 |
Popis: | Hardware failures are undesired but a common problem in circuits. Such failures are inherently due to the aging of circuitry or variation in circumstances. In critical systems, customers demand the system never to fail. Several self-healing and fault tolerance techniques have been proposed in the literature for recovering a circuitry from a fault. Such techniques come to the rescue when a fault has already occurred but they are typically uninformed about the possibility of an impending failure (i.e., fault prediction), which can be used as a pre-stage to fault tolerance and self-healing. This paper presents an approach to early fault prediction of circuits. The proposed method uses Fast Fourier Transform (FFT) to get the fault frequency signature, Principal Component Analysis (PCA) to get the most important data with reduced dimension, and Convolutional Neural Network (CNN) to learn and classify the fault. The proposed method is validated for working in different circuits by testing it using two circuits: comparator and amplifier. The comparator and amplifier are implemented using 45 nm technology on HSPICE to extract the failures dataset in terms of voltage, current, temperature, noise, and delay. This extracted data is used for training the proposed approach using Tensorflow. To the best of our knowledge, this is the first work of fault prediction at the transistor level for hardware system. The proposed approach considers aging, short-circuit, and open-circuit faults, and it provides a fault prediction accuracy of 98.93% and 98.91% for comparator and amplifier circuits, respectively. The proposed method is tested for two different circuits for its validation, and it consumes 1.08 W for Altera Arria 10 GX FPGA device. |
Databáze: | OpenAIRE |
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