A 1mm2 1.3mW GSM/EDGE digital baseband receiver ASIC in 0.13 µm CMOS

Autor:	A. Bubenhofer, Qiuting Huang, C. Benkeser
Rok vydání:	2010
Předmět:	Engineering business.industry CMOS Application-specific integrated circuit Modulation GSM Hardware_INTEGRATEDCIRCUITS Baseband Electronic engineering Enhanced Data Rates for GSM Evolution General Packet Radio Service business Computer hardware Data transmission
Zdroj:	VLSI-SoC
Popis:	This paper addresses complexity issues at algorithmic and architectural level of digital baseband receiver ASIC design for GSM/GPRS/EDGE, in order to reduce power and die area as desired for cellular applications. A 2.5G multi-mode architecture is implemented in 0.13 µm CMOS technology occupying 1.0mm2 and dissipating only 1.3mW in fastest EDGE data transmission mode.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::11b49411ff62fce30093e2919ed8c53f https://doi.org/10.1109/vlsisoc.2010.5642592 Zobrazit plný text záznamu