A 1mm2 1.3mW GSM/EDGE digital baseband receiver ASIC in 0.13 µm CMOS
Autor: | A. Bubenhofer, Qiuting Huang, C. Benkeser |
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Rok vydání: | 2010 |
Předmět: | |
Zdroj: | VLSI-SoC |
Popis: | This paper addresses complexity issues at algorithmic and architectural level of digital baseband receiver ASIC design for GSM/GPRS/EDGE, in order to reduce power and die area as desired for cellular applications. A 2.5G multi-mode architecture is implemented in 0.13 µm CMOS technology occupying 1.0mm2 and dissipating only 1.3mW in fastest EDGE data transmission mode. |
Databáze: | OpenAIRE |
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