A dynamic three-state memory cell for high-density associative processors
| Autor: | K. Ishio, F.P. Herrmann, C.L. Keast, J.P. Wade, Charles G. Sodini |
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| Rok vydání: | 1991 |
| Předmět: |
Random access memory
business.industry Computer science Transistor Hardware_PERFORMANCEANDRELIABILITY law.invention Read-write memory CMOS Memory cell law Hardware_INTEGRATEDCIRCUITS Content-addressable storage Node (circuits) State (computer science) Central processing unit Electrical and Electronic Engineering business Computer hardware Hardware_LOGICDESIGN |
| Zdroj: | IEEE Journal of Solid-State Circuits. 26:537-541 |
| ISSN: | 0018-9200 |
| DOI: | 10.1109/4.75051 |
| Popis: | A dynamic associative processor cell is described. The cell stores three states (0, 1, and X) and performs read, match, and masked-write functions. Five MOS transistors are used, including two overlapping dual-gate structures available in MIT's CCD/CMOS technology. Dual-gate CCD transistors are used to reduce the charge-spooning current, which can discharge the storage node through the write transistors. The use of the cell in an associative processor is described, and experimental results are presented. > |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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