Circuit-Level Impact of a-Si:H Thin-Film-Transistor Degradation Effects
| Autor: | Zhiwei Li, Sameer M. Venugopal, Shawn M. O'Rourke, Edward J. Bawolek, S.G. Uppili, R. Shringarpure, H. Shivalingaiah, David R. Allee, Bryan D. Vogt, J.J. Ravindra Fernando, Lawrence T. Clark, Korhan Kaftanoglu |
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| Rok vydání: | 2009 |
| Předmět: |
Amorphous silicon
Negative-bias temperature instability Materials science business.industry Transistor Electronic Optical and Magnetic Materials PMOS logic Amorphous solid law.invention chemistry.chemical_compound chemistry law Thin-film transistor MOSFET Electronic engineering Optoelectronics Field-effect transistor Electrical and Electronic Engineering business |
| Zdroj: | IEEE Transactions on Electron Devices. |
| ISSN: | 0018-9383 |
| DOI: | 10.1109/ted.2009.2019387 |
| Popis: | This paper reviews amorphous silicon thin-film-transistor (TFT) degradation with electrical stress, examining the implications for various types of circuitry. Experimental measurements on active-matrix backplanes, integrated a-Si:H column drivers, and a-Si:H digital circuitry are performed. Circuit modeling that enables the prediction of complex-circuit degradation is described. The similarity of degradation in amorphous silicon to negative bias temperature instability in crystalline PMOS FETs is discussed as well as approaches in reducing the TFT degradation effects. Experimental electrical-stress-induced degradation results in controlled humidity environments are also presented. |
| Databáze: | OpenAIRE |
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