| Autor: |
Y. Amar Babu, John Bedford Solomon, G. M. V. Prasad |
| Rok vydání: |
2017 |
| Předmět: |
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| Zdroj: |
Advances in Intelligent Systems and Computing ISBN: 9789811068744 |
| DOI: |
10.1007/978-981-10-6875-1_55 |
| Popis: |
Transistor size shrinking day-to-day as technology node moves towards deep sub nano meter node so, Interconnects dominate overall performance of system-on-chip. Conventional shared bus architecture could not handle on-chip communication issues like bandwidth, power consumption, and signal integrity. To overcome these issues network-on-chip provides the best alternative to shared bus architectures. In this paper, novel NoC router has been proposed to minimize area design metric to 50% and power consumption for efficient on-chip hybrid communication in the spatial division multiplexing-based network-on-chip. Using proposed NoC router a 2 × 2 SDM-based NoC has been implemented on Xilinx Spartan 6 FPGA and performance are evaluated and compared with TDM-based NoC architectures. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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