A CMOS Low-Power 10:4 MUX and 4:10 DEMUX Gearbox IC for 100-Gigabit Ethernet Link
| Autor: | Ryo Nemoto, Fumio Yuki, Hiroki Yamashita, Masayoshi Yagyu, Noboru Masuda, Hidehiro Toyoda, Takashi Muto, Tatsuya Saito, Koji Fukuda, Seiichi Umai, Shinji Nishimura, Takashi Takemoto, Goichi Ono, K. Watanabe, Masashi Kono, Eiichi Suzuki, Akihiro Kambe |
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| Rok vydání: | 2011 |
| Předmět: |
Engineering
business.industry Electrical engineering Hardware_PERFORMANCEANDRELIABILITY Integrated circuit design Multiplexer Power (physics) 100 Gigabit Ethernet Phase-locked loop S interface CMOS Low-power electronics Hardware_INTEGRATEDCIRCUITS Electronic engineering business Hardware_LOGICDESIGN |
| Zdroj: | 2011 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS). |
| DOI: | 10.1109/csics.2011.6062438 |
| Popis: | The world's first CMOS "gearbox LSI" based on 65-nm CMOS technology-namely, a 2-W 100-gigabit-Ethernet gearbox LSI combining a 10:4 multiplexer and a 4:10 demultiplexer-was developed. Its power consumption is 75% lower than that of a conventional SiGe-based gearbox LSI. The power consumption of its 12.5-Gb/s interface is 0.98 mW/(Gb/s), while that of its 25- Gb/s interface is 14 mW/(Gb/s). |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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