| Autor: |
W.V. Herrick, J.F. Brown, D.R. Deverell, Elizabeth M. Cooper, T.C. Fischer, G.M. Uhler, Hamid Partovi, R.I. Bahar, M.A. Case, M.A. Delaney, V. Peng, A. Jain, J.E. Meyer, J.J. Ellis, R.P. Preston, M.K. Gowan, D. Bernstein, T.F. Fox, D.G. Miner, C. Somanathan, R.L. Stamm, R.W. Badeau, W.R. Wheeler, N.D. Wade, J.H. Edmonson, S.C. Thierauf, R.W. Castelino, L.L. Biro, W.J. Bowhill, P.E. Gronowski |
| Rok vydání: |
1992 |
| Předmět: |
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| Zdroj: |
IEEE Journal of Solid-State Circuits. 27:1585-1598 |
| ISSN: |
0018-9200 |
| DOI: |
10.1109/4.165340 |
| Popis: |
A macropipelined CISC microprocessor was implemented in a 0.75- mu m CMOS 3.3-V technology. The 1.3-million-transistor custom chip measures 1.62*1.46 cm/sup 2/ and dissipates 16.3 W. The 100-MHz parts were benchmarked at 50 SPEC marks. The on-chip clocking system and several high-performance logic and circuit techniques are described. Macroinstruction handling, micropipeline management, and control store structures highlight the design architecture. The hierarchical array organization and fast tag comparison technique of the primary cache are discussed. Power estimation procedures are outlined, and the results are compared to measurements. Physical design and verification methods, and CAD tools are also described. After extensive functional verification efforts are described, chip and system test results are presented. > |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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