| Autor: |
Bertrand Borot, Hassen Aziza, J.-M. Portal, F. Rigaud, Fabrice Argoud, J. Vast, D. Nee |
| Rok vydání: |
2008 |
| Předmět: |
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| Zdroj: |
2008 IEEE International Conference on Microelectronic Test Structures. |
| DOI: |
10.1109/icmts.2008.4509313 |
| Popis: |
The objective of this paper is to present a mixed test structure designed to characterize yield losses due to hard defect and back-end process variation (PV) at die and wafer level. A brief overview of the structure, designed in a ST-Microelectronics' 130 nm technology, is given. This structure is based on a SRAM memory array for detecting hard defects. Moreover each memory cell can be configured in the ring oscillator (RO) mode for back-end PV's characterization. The structure is tested in both modes (SRAM, RO) using a single test flow. Experimental results are given and confirm the ability of the structure to monitor PV and defect density. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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