| Autor: |
Ji-Hoon Lim, Hong-June Park, Kihwan Seong, Jae-Yoon Sim, Byungsub Kim |
| Rok vydání: |
2014 |
| Předmět: |
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| Zdroj: |
JSTS:Journal of Semiconductor Technology and Science. 14:463-470 |
| ISSN: |
1598-1657 |
| DOI: |
10.5573/jsts.2014.14.4.463 |
| Popis: |
A Verilog model is proposed for transmission lines to perform the all-Verilog simulation of high-speed chip-to-chip interface system, which reduces the simulation time by around 770 times compared to the mixed-mode simulation. The single-pulse response of transmission line in SPICE model is converted into that in Verilog model by converting the full-scale analog signal into an 11-bit digital code after uniform time sampling. The receiver waveform of transmission line is calculated by adding or subtracting the single-pulse response in Verilog model depending on the transmitting digital code values with appropriate time delay. The application of this work to a USB 2.0 high-speed PHY interface reduces the simulation time to less than three minutes with error less than 5% while the mixed-mode simulation takes more than two days for the same |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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