On the Design of Modulo 2 n ±1 Subtractors and Adders/Subtractors

Autor:	D. Bakalis, Haridimos T. Vergos, Evangelos Vassalos
Rok vydání:	2011
Předmět:	Combinational logic Discrete mathematics Adder Applied Mathematics Modulo Signal Processing Cmos vlsi Hardware_ARITHMETICANDLOGICSTRUCTURES Arithmetic Operand Completeness (statistics) Residue number system Mathematics
Zdroj:	Circuits, Systems, and Signal Processing. 30:1445-1461
ISSN:	1531-5878 0278-081X
DOI:	10.1007/s00034-011-9326-5
Popis:	Novel architectures for designing modulo 2 n +1 subtractors and combined adders/subtractors are proposed in this manuscript. Both the normal and the diminished-one representations of the operands are considered. Unit gate estimates and CMOS VLSI implementations reveal that the proposed modulo 2 n +1 subtractors for operands in the normal representation are more efficient than those previously proposed. The proposed diminished-one modulo 2 n +1 subtractors have a complexity similar to that of the corresponding diminished-one adders. Modulo 2 n −1 subtractors and adders/subtractors are also considered for the sake of completeness and a comparison between alternative architectures is provided.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::0f3881e73255f4f1313f336083d9dcfc https://doi.org/10.1007/s00034-011-9326-5 Zobrazit plný text záznamu Full text from SpringerLink