| Popis: |
Conventional carry select adder (CCSA) uses a multiplexer in the final stage to select either an excess-1 result or a normal result. To improve the delay and number of transistors a new topology is Proposed (PCSA) that uses only a single type of cell i.e., a 2 − 1 multiplexer. The 2 − 1 multiplexer is constructed in CMOS and TGL logic styles using 18nm FinFETs. The sub-blocks such as half adder and excess-1 circuit used in this PCSA is realized using only a 2:1 multiplexer. Due to the usage of a single type 2:1 multiplexer, the PCSA exhibits better circuit regularity. The new topology of PCSA is designed using FinFET-based TGL and CMOS styles. All the adders such 4- and 8-bit are designed, simulated, and analyzed using Cadence Virtuoso, ADEL, and ADEXL at 18nm FinFET technology. The result analysis reveals that the speed performance and the number of transistors of 8-bit PCSA are better by 44.02% and 4% respectively compared to existing adders. |
