| Autor: |
Gerald George Pechanek, Nikos P. Pitsianis |
| Rok vydání: |
2003 |
| Předmět: |
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| Zdroj: |
ACM SIGARCH Computer Architecture News. 31:69-74 |
| ISSN: |
0163-5964 |
| DOI: |
10.1145/773365.773373 |
| Popis: |
The indirect very long instruction word (iVLIW) architecture and its implementation on the BOPS ManArray family of multiprocessor digital signal processors (DSP) provides a scalable alternative to the wide instruction busses usually required in a multiprocessor VLIW DSP. The ManArray processors indirectly access VLIWs from small caches of VLIWs localized in each processing element. With this work, we present an algorithm to perform 1) iVLIW instruction memory allocation on multiple processing elements to minimize instruction memory requirements and 2) scheduling of the iVLIW setup instructions to minimize execution overhead. We present preliminary experimental results that demonstrate the effectiveness of our approach. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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