Design of low power high speed full adder cell with XOR/XNOR logic gates
| Autor: | Sudhakar Alluri, M. Dasharatha, N. S. S. Reddy, B. Rajendra Naik |
|---|---|
| Rok vydání: | 2016 |
| Předmět: |
Very-large-scale integration
Adder AND-OR-Invert Pass transistor logic Computer science business.industry Transistor Electrical engineering 020206 networking & telecommunications Hardware_PERFORMANCEANDRELIABILITY 02 engineering and technology law.invention Power (physics) XNOR gate law Logic gate Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering 020201 artificial intelligence & image processing Hardware_ARITHMETICANDLOGICSTRUCTURES business Hardware_LOGICDESIGN |
| Zdroj: | 2016 International Conference on Communication and Signal Processing (ICCSP). |
| DOI: | 10.1109/iccsp.2016.7754203 |
| Popis: | This present paper, a 3 transistor XNOR gate is proposed. The proposed XNOR gate is designed using CADENCE EDA tool and simulated using the SPECTRE VIRTUOSO at 180 nm technology. The proposed results are compared with the previous existing designs in terms of power and delay. It is observed that the power consumption is reduced by 65.19 % for three transistor XNOR gate and 48.11% for eight transistor full adder. It is also observed that the delay is reduced by 31.82% for three transistors XNOR gate and 28.76% for eight transistors full adder. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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