An Area Efficient FFT Processor using Modified Compressor adder based Vedic Multiplier

Autor:	S. Dhanasekar, P. Malin Bruntha, L. Jubair Ahmed, G. Valarmathi, V. Govindaraj, C. Priya
Rok vydání:	2022
Zdroj:	2022 6th International Conference on Devices, Circuits and Systems (ICDCS).
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::0e5ef146df89b0fd722af08494a24355 https://doi.org/10.1109/icdcs54290.2022.9780676 Zobrazit plný text záznamu