A Fully Integrated Asymmetrical Shunt Switched-Capacitor DC–DC Converter With Fast Optimum Ratio Searching Scheme for Load Transient Enhancement
| Autor: | Shian-Ru Lin, Yen-Ting Lin, Tsung-Yen Tsai, Yu-Sheng Ma, Ke-Horng Chen, Yan-Jiun Lai, Hung-Wei Chen, Wen-Hau Yang, Ying-Hsi Lin |
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| Rok vydání: | 2019 |
| Předmět: |
Materials science
020208 electrical & electronic engineering 02 engineering and technology Converters Switched capacitor Transient voltage suppressor law.invention Capacitor Parasitic capacitance law Control theory 0202 electrical engineering electronic engineering information engineering Output impedance Electrical and Electronic Engineering Electrical efficiency Voltage |
| Zdroj: | IEEE Transactions on Power Electronics. 34:9146-9157 |
| ISSN: | 1941-0107 0885-8993 |
| DOI: | 10.1109/tpel.2018.2889870 |
| Popis: | This paper presents a modified negator-based switched-capacitor (NSC) dc–dc converter to achieve fine-grained voltage conversion ratios. Based on a concept of reconfiguring several 2:1 switched-capacitor (SC) converters in series and parallel at the last stage, the proposed asymmetrical shunt SC (ASSC) converter provides more controllable variables of forward gain and feedback gain to decide different power path interconnections and increase the available conversion ratios, with a little sacrifice of its slow switching limit output impedance. The switching loss of the bottom-plate parasitic capacitance in the ASSC converter is less than the switching loss of the NSC topology because the two moderate voltages instead of the power rail are fed to the last stage 2:1 SC unit and reduce the voltage swing. The bottom-plate swapping prototype further reduces the parasitic loss at high conversion ratios. To handle a large number of conversion ratios in closed-loop regulation, the ASSC converter uses the fast optimum ratio searching (FORS) technique, which evaluates the transient voltage drop to quickly search for target ratios and reduce the transient recovery time. A three-stage ASSC converter achieving 187 conversion ratios is fully integrated in the test chip, which is fabricated in 0.25-μm CMOS process with an active area of 7.14 mm2. Furthermore, 2389 conversion ratios can be derived in theory for a four-stage ASSC converter. The proposed reconfigurable SC converter provides an output voltage range of 0.4 to 2.8 V under no load conditions, and greater than 80% power efficiency at an output voltage level of 0.9 to 1.5 V over a load range of 3 to 9.5 mA. Due to the FORS technique, the measured transient recovery time is reduced from 7 to 1.5 μs in case of load current step of 7 mA. |
| Databáze: | OpenAIRE |
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