An Assessment of Electromigration in 2.5D Packaging
Autor: | Gamal Refai-Ahmed, Vanlai Pham, Jiefeng Xu, Seungbae Park, Scott McCann, Jing Wang, Huayan Wang, Stephen R. Cain |
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Rok vydání: | 2019 |
Předmět: |
010302 applied physics
Interconnection Materials science chemistry.chemical_element 02 engineering and technology 021001 nanoscience & nanotechnology 01 natural sciences Copper Electromigration Line (electrical engineering) Substrate (building) chemistry Ball grid array 0103 physical sciences Composite material 0210 nano-technology Current density Voltage |
Zdroj: | 2019 IEEE 69th Electronic Components and Technology Conference (ECTC). |
DOI: | 10.1109/ectc.2019.00-25 |
Popis: | In this study, an accelerated Electromigration (EM) test was performed. The test vehicle has four types of common interconnect structure. The first one is a classic Ball Grid Array (BGA), short for BGA; the second one is a solder ball with a copper via on top, short for BGA-Via; the third one is an individual copper via in the substrate, short for Via; the last one is an individual copper Plated Through Hole (PTH), short for PTH in the substrate. The built-in serpentine copper fine lines around each structure were designed to monitor the local temperature in-situ. All test vehicles were stressed at 150oC temperature with 12A current. The voltage of each test structure and the resistance of the serpentine line were recorded in-situ. The results show that different micro-electrical structures have great effects on EM behavior, especially the time to failure (TTF). In BGA test structure, the failure occurred on the substrate side of solder ball; in BGA-Via, the failure was the depletion of the copper via. No failure was observed in Via and PTH test structures, even after an extremely long testing, although they have higher package temperature. The TTF of BGA-Via is about 2 times shorter than BGA. A finite element simulation based on Atom Flux Divergence (AFD) was performed to understand the failure mechanism and predict the TTF. The results show that via on top of solder ball will cause 10% higher current density than solder ball only. When the void underneath of the via in solder ball was nucleated, the current density will start to redistribute and reduce. In short, Via is the riskiest point for EM when it located near the solder ball. |
Databáze: | OpenAIRE |
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